This article is the third in a series of silicon photonics write-ups over on Semiconductor Insider. In this segment, we’re explaining (hopefully in easy-to-understand language) Nvidia (NVDA) and Taiwan Semiconductor Manufacturing’s (TSM) silicon photonics breakthrough: Co-packaged optics (CPO) in Nvidia’s AI data center switching devices.
TSMC has been steadily growing its manufacturing empire into new domains, including “packaging” of various kinds. Silicon photonics is one of those areas. In fact, TSMC has been publishing papers on silicon photonics for years now. https://ieeexplore.ieee.org/document/9501846/ https://research.tsmc.com/page/on-chip-interconnect/21.html
So none of this is really a surprise that Nvidia announced new silicon photonics based products at GTC this year, with TSMC being the primary manufacturing partner.
What does TSMC’s photonics manufacturing look like?
The commentary and opening picture from Jensen during the photonics segment of GTC, in Kasey’s words, “had a LOT going on.”
Let’s break it down, using Nvidia’s excellent video outlining the engineering and manufacturing marvel that is co-packaged optics (CPO) for advanced networking. We’ll start with an outside view of the Nvidia Quantum-X (that’s the proprietary InfiniBand-based networking product, vs the Spectrum-X product line which is the open standards Ethernet-based).
By way of review, these “switches” are used to interconnect thousands, and one day very soon, millions of GPUs together.
Under the hood of Nvidia’s new CPO product lines
First, we’ll rip off the top of the Quantum-X server shown above. Directly under the hood, Nvidia labels the whole device’s control module, and next to it, lines for running liquid cooling to the chips underneath.
Remember the Semi Industry Flow video on IP, and how companies like Nvidia can monetize the entire supply chain now – including liquid cooling parts of the server made by companies like Vertiv (VRT)? See that breakdown here: How to Invest In Chip Stocks 2025: Semiconductor IP — Tiny Tech, Big Bucks!
Let’s continue. Next we’ll pull those liquid cooling devices and coolant lines out of the box to see what’s underneath.
Notice how many chips are crammed into these packages: One Quantum-X800 ASIC (application specific integrated circuit), 6 optical sub-assemblies, and 18 photonics engines. No wonder new cooling methods are needed. That’s a lot of electrical parts in a small space, all of them drawing power and putting off heat!
Here’s a closer look at the Quantum-X800 ASIC. The chip is made using TSMC’s N4 manufacturing node (N3 is currently the most advanced manufacturing process in full production, with N2 getting ready to ramp up later this year).
What exactly does this Quantum-X800 ASIC do? The overall devices we’re discussing are called “switches.” They help coordinate the movement of, and move around all of the data that flows through a data center. In this case, we’re talking about many thousands of GPUs stitched together to train or operate an AI model. These Quantum-X chips help coordinate all the traffic, kind of like a freeway’s interchanges, onramps, and offramps.
Let’s complete that visual. Here’s the Quantum-X ASIC with the optical cables (like lanes on the freeway) plugged into it.
Now, each of those optical plugs plugged into the Quantum-X ASIC like it’s Frankenstein’s monster are no simple feat either.
Let’s pull one of those plugs (the sub-assembly) apart as well and see what’s inside. You guessed it… more “chips” are inside.
What’s TSMC’s silicon photonics manufacturing got to do with it?
Up to this point, we’ve only mentioned TSMC’s N4 process used to fab the Quantum-X800 ASIC. But that particular chip is a type of processor. There’s no silicon photonics manufacturing going on there.
But it’s inside the optical sub-assembly plug that this new “photonics engine” makes its appearance. This is where Nvidia and TSMC went out and got some IP/patent help, and maybe even some manufacturing help, from the photonics IDMs like Coherent and Lumentum.
But this is where the new engineering (Nvidia, likely by way of Mellanox acquired in early 2020) and manufacturing (TSMC and its equipment suppliers) come into play. Look at the “photonics engine” itself. That’s a new type of chip that makes use of a “micro-ring modulator” (or MRM) — basically, an MRM is used with other tiny components in reading the signal of light transmitted via the optical cable, and converts the laser pulses of light into digital code of 1s and 0s.
Beneath the MRM, other “chips” are vertically stacked, and underneath that is the layers of silicon and other substrate, including the final packaging for the entire module.
In layperson’s terms, this is a really complex freeway onramp/offramp – but instead of cars, it’s for data flowing to and from the GPUs that are training or running the AI.
But wait, there’s more! If you can handle it. The “photonics engine” can be further dissected. This is what Jensen alluded to as TSMC’s “COUPE” manufacturing platform – COUPE being yet another acronym for “COmpact Universal Photonics Engine.” At this stage, COUPE is utilizing TSMC’s N6 manufacturing node, which ramped up production back in 2020.
Let’s get some more detail on the side-view schematic of this COUPE device. This is where TSMC’s advanced packaging prowess comes into play. See the multiple vertically-stacked layers of “chips” handling different functions? There’s a separate layer for the photonics (the silicon that interacts with the pulses of laser light) and a layer for the electronics (the part that deals with the 1s and 0s of digital code).
Now that we’ve taken a tour of Nvidia’s co-packaged optics (CPO) utilizing TSMC COUPE, we can zoom back out to the cables themselves. SOOO. MUCH. CABLE!!! Oh yeah, and also “freakin’ laser beams!” (Accompanying Dr. Evil GIFs are a Semi Insider Discord exclusive.🙂)
A new “era” for silicon photonics and CPO have dawned. Congrats to the amazing teams at Nvidia and TSMC, and all of their critical supply chain partners, for pulling this feat of engineering off!
