But before that, due to a number of questions, we thought we would upload our research notes with the slides from the CSI Live presentation a couple weeks ago regarding Intel (INTC) EMIB vs. TSMC‘s (TSM) CoWoS advanced packaging processes. Enjoy!
Where is resurgent Intel optimism coming from?
What is happening at Intel, where is the optimism coming from? Besides the injections of cash, including from the U.S. government, much of it has to do with advanced packaging manufacturing.
Intel is traditionally an IDM, but now offers external customers a foundry service to compete with TSMC.
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The Intel 18A wafer manufacturing line is finally making a bit of progress, but…
Catching up in front-end wafer development was never going to cut it for Intel. That was the crux of the argument here at CSI all along. Companies “catch up” to the leaders when there’s a shift in technology, the leader makes a massive mistake, or a combination of both. “No moats, only fastest cars.”
There is a narrow opening on the advanced packaging side, advanced packaging being one of our original points to the (at the time) possible new bull market all the way back in 2022.
So we are not going to be discussing Intel’s financials. Lets talk about the tech. We have already talked plenty about Intel’s financial validation not being there yet.
A bit of terminology
We often talk about data center networking (switches and routers) as like the freeway interchange and onramp / offramp system. What about all of the city surface streets — the small metal wires and interconnects within a chip and its packaging (circuit board and related)?
- CoWoS: Chip-on-Wafer-on-Substrate; one of TSMC’s family of advanced packaging processes; like a grid of surface streets for local transit (home to office, home to store, etc.).
- EMIB: Embedded Multi-die Interconnect Bridge; one of Intel’s family of advanced packaging processes; like a main street or direct tunnel or bridge between locations.
TSMC CoWoS and its -S, -R, and -L variations
First, some more specific terminology as pertains to TSMC:
- Interposer: An intermediary substrate, usually silicon, with smaller metal traces for routing data; sits between the chips (and/or chiplets) and the circuit board (PCB, main substrate).
- RDL: Redistribution layer, an extra insulated layer with smaller denser wiring to re-route I/O between chip and interposer.
- LSI: Local silicon interconnect, a “bridge” with very small and dense wiring for chip-to-chip connections that bypass the interposer; similar in design to Intel’s EMIB.
CoWoS-S: Very complex to manufacture and not super efficient. Slab of silicon between chips and substrate. Like travelling block by block, street by street to the store.
CoWoS-R: You still have the silicon interposer, but there’s an RDL between the chips and the interposer. A way to redistribute the input/output directly to the chip and attach to a smaller or simpler interposer underneath that. Has some advantages in manufacturing simplicity and ultimately performance.
CoWoS-L: The newest tech, kind of gets TSMC a bit closer to the Intel EMIB. Still an interposer between the chips and substrate, and still using the RDL to route the I/O to the chips. They have introduced an LSI, local silicon interconnect, like a bridge or tunnel for chip to chip communication, without having to run those interconnects directly through the interposer.
Hello Intel EMIB, goodbye silicon interposer
Some terminology as it pertains to Intel:
- MIM: Metal-Insulator-Metal capacitor, or simply “M”; embedded within EMIB bridge to help with power delivery.
- TSV: Through-Silicon Vias, or simply “T”; added TSVs with MIM within EMIB for better vertical power and data delivery.
- Foveros: Intel’s vertical stacking (2.5D and 3D) packaging technology for chiplet-based designs; foveros = awesome or amazing in Greek.
Intel’s EMIB has no interposer. Intel has its own in house OSAT. OSAT = Outsource semiconductor assembly and test.
As result of that, after Intel gets its PCBs from suppliers, they carve out a channel and make an EMIB device in that carved-out channel.
Where CoWos uses an interposer, Intel’s EMIB process is all contained within the channels of the circuit board.
There are a couple different versions, the original EMIB has been in small production for a decade, but Intel has made improvements (the “M” and “T” from the below slide).
A couple more iterations of what this looks like in the slide below. Intel pairs this newer EMIB process with their Foveros 3-D stacking, the equivalent at TSMC of SoIC (system on integrated chip) advanced packaging.
Why is this important? Is a door possibly opening for Intel?
Remember we said “catching up” to an established leader often requires a shift in technology, and maybe a mistake from the incumbent? Advanced packaging is that shift. Is there a TSMC mistake to go with it? Depends on what you consider to be a “mistake.”
Nvidia owns the AI training market. There is essentially no one else. And it uses up most of TSMC’s CoWoS capacity.
In AI inference, Nvidia competes with everyone else with GPUs, CPUs, NVLink Fusion (integrating ASICs into Nvidia architecture), LPUs, etc. And many of these diverse hardware architectures could benefit from more choice in advanced packaging. That’s where advanced packaging capacity availability at Intel comes in, and why numerous reports suggest big tech is in various stages of qualifying Intel as a foundry — if not for volume orders of new devices, than at least as a second supplier for supply chain resiliency.
The more fragmented AI inference market is one of many reasons why Nvidia stock trades at a relative value, and why Intel and other stock ran higher in the last year.
In summary, why has Intel stock raced higher?
- Intel got key investments from U.S. govt. and Nvidia to shore up the balance sheet.
- The “CPU shortage” (refresh cycle + growth CapEx cycle for AI) was a lifeline that helped stabilize revenue and stem cash flow losses.
- Advanced packaging is helping jumpstart more customer interest in Intel Foundry.
- Tight TSMC capacity has customers searching for more suppliers to meet their semiconductor infrastructure demand.
The natural progression of a bull market
As the bull market ages and more companies join in on the party, studying the tech and “what layer is next” becomes less important. Allocate the capital, manage your risk, and increasingly focus your attention on the durability of company earnings potential, health of their balance sheet, etc.
In other words, who is preparing financially not just for the next thing in tech, but also a future cycle downturn — or even a future bear market.
Intel, TSMC, and others are the world’s largest and most valuable manufacturers (industrialists, not just information technology sector participants). Capital intensity is high, and return-on-investment is critical. The advanced packing race isn’t over. These companies change slowly, not in a one- to two-year turnaround miracle.
Nevertheless, this battle is an important one, and worth monitoring closely. And it is likely to continue well into the 2030s.
